module zl_2346_7_2(cp,c);
input cp;
output reg c = 1;
parameter num = 500;//    50MHz/100kHz

reg[7:0] cnt = 0;//偶分频计数器

always @(posedge cp)
begin
	if(cnt<num/2-1)begin
		cnt <= cnt+1'b1;
		c <= c;
	end
	else
	begin 
		cnt <= 8'd0;
		c <= ~c;
	end
end

endmodule
